The present invention relates to an erasing method for a nonvolatile semiconductor memory device, and more particularly, to an erasing method for a nonvolatile semiconductor memory device which makes it possible to improve a threshold voltage distribution after executed an erasing operation in the nonvolatile semiconductor memory device employing a writing method with use of channel hot electrons.
As a most commonly used flash memory, there has conventionally been an ETOX (EPROM THIN OXIDE: Trademark of Intel Co.). A schematic cross sectional view of this ETOX-type flash memory cell is shown in FIG. 9. As shown in FIG. 9, on a source 1, a drain 2, and a substrate (well) 3 between the source and the drain, there is formed a floating gate 5 with a tunnel oxide 4 interposed. Further on the floating gate 5, there is formed a control gate 7 with an interlayer insulating film 6 interposed.
Description will be now given of an operational principle of the ETOX-type flash memory. In a writing operation, as shown in Table 1, a voltage Vpp (ex., 10V) is applied to the control gate 7, a reference voltage Vss (ex., 0V) is applied to the source 1, and a voltage of 6V is applied to the drain 2. Consequently, a large current flows through a channel layer, and hot electrons are generated in an area with high electric fields on the drain 2 side, by which electrons are injected into the floating gate 5. As a result, a threshold voltage is increased and writing onto a certain memory cell is executed. FIG. 10 shows a threshold voltage distribution in a written state and in an erased state. As shown in FIG. 10, threshold voltages of memory cells in the write state are 5V or more.
In an erasing operation, as shown in FIG. 11, a voltage Vnn (ex., xe2x88x929V) is applied to the control gate 7, a voltage Vpe (ex., 4V) is applied to the source 1, and the drain 2 is set to be open, so that electrons are pulled toward the source 1 side and the threshold voltage is decreased. As a result, as shown in FIG. 10, the threshold voltages of memory cells in an erased state are 0.5V to 3V. In this case, a BTBT (Band To Band Tunneling) current flows from the source 1 to the Substrate (well) 3. Upon generation of this current, hot holes and hot electrons are also generated. The hot electrons flow away to the drain 2, whereas the hot holes are pulled toward the tunnel oxide 4 side and trapped inside the tunnel oxide 4. Generally, this phenomenon is considered to be a cause of deteriorated reliability.
In a reading operation, a voltage of 1V is applied to the drain 2, and a voltage of 5V is applied to the control gate 7. Herein, if a memory cell is in an erased state and low in the threshold voltage, current flows into the memory cell and status of the memory cell is determined to be xe2x80x9c1xe2x80x9d. If the memory cell is in a written state and high in the threshold voltage, current does not flow into the memory cell, and status of the memory cell is determined to be xe2x80x9c0xe2x80x9d.
As described above, the operation with use of applied voltages shown in Table 1 has a problem that a BTBT current generated in the erasing operation causes deteriorated reliability of the memory cells. As one solution of this problem, there is a method of conducting, at the time of erasing, a channel erasing operation which does not generate the BTBT current. Herein, the erasing operation that pulls electrons toward the source 1 side as described above is called a xe2x80x9csource-side erasing operationxe2x80x9d. It is noted that a writing operation and a reading operation in the case of conducting the channel erasing operation are identical to the case of conducting the source-side erasing operation.
Hereinbelow, description will be made of the channel erasing operation. Table 2 shows voltage application conditions in each writing, erasing, and reading access to ETOX-type flash memory cells in the case of conducting the channel erasing operation.
In the above channel erasing, as shown in FIG. 12, a voltage Vnn (ex., xe2x88x929V) is applied to the control gate 7, and a voltage Vesc (ex., +7V) is applied to the source 1 and a first well (p well) 8. Consequently, strong electric fields are applied to the tunnel oxide 4 disposed between a channel layer and the floating gate 5, and due to an FN (Fowler-Nordheim) tunneling phenomenon, electrons are pulled from the floating gate 5 toward the channel side, resulting in decrease of the threshold voltage. As shown in FIG. 10, a threshold voltage distribution in a written and an erased state is approximately identical to that in the source-side erasing operation.
In this case, potential of the source 1 is equal to potential of the first well (p well: channel region) 8, so that electric fields are not concentrated onto an interface between the source 1 and the well 8, and therefore the BTBT current is not generated. As a result, hot hole trap is not generated, resulting in improved reliability of the memory cells.
However, the above-described channel erasing operation has a problem that dispersion in the threshold voltage distribution after an erasing operation, attributed to dispersion of a channel length, is larger than that in the source-side erasing operation, as indicated in xe2x80x9cComparison of Current Flash EEPROM Erasing Methods: Stability and How to controlxe2x80x9d IEDM Tech. Dig 1992 IEDM 92-595 (reference 1). Therefore, the channel erasing operation requires control of dispersion in the threshold voltage after executed the erasing operation.
As one solution to this problem, there is a method disclosed in xe2x80x9cControl of Erased Flash Memory""s Threshold Voltage by 2-Step Erasing Schemexe2x80x9d, Technical Report SDM93-29 1993 of Institute of Telecommunications Engineers (reference 2). Applying this method to a memory cell structure of FIG. 12 results in applied voltage waveforms shown in FIG. 13. As shown in FIG. 13, the two-step erasing method is made up of a first step and a second step. In the first step, a voltage Vnn (ex., xe2x88x929V) is applied to the control gate 7, and a voltage Vesc (ex., +7V) is applied to the source 1 and the first well (channel region) 8. In the second step, a voltage Vpcg (ex., 10V) is applied to the control gate 7, and a voltage Vpsc (ex., xe2x88x927V) is applied to the source 1 and the first well (channel region) 8. An operation in the first step is identical to the normal channel erasing operation shown in FIG. 12, where the threshold voltage is decreased by the erasing operation. On the other hand, an operation in the second step is, as shown in FIG. 14, to inject electrons from a channel layer 10 into the floating gate 5 for increasing the threshold voltage. More particularly, some writing is executed to decrease dispersion in the threshold voltage of the memory cells. Hereinafter, a writing operation shown in FIG. 14 is referred to as a xe2x80x9cchannel writing operationxe2x80x9d.
FIG. 15 shows a change in the threshold voltage distribution in the tow-step erasing operation. Comparison between the change in the threshold voltage distribution in FIG. 15 and that in the normal channel erasing operation of FIG. 10 clarifies that the width of the threshold voltage distribution in the erased state is narrow and tight with the two-step erasing method. This indicates that the two-step erasing method is effective for achieving a tight threshold voltage distribution after executed the erasing operation.
The following description discusses a mechanism of the phenomenon shown in FIG. 15 with reference to FIGS. 16 and 17, and a model equation of the FN tunnel current (for detail, see the reference 2). The FN tunnel current JFN is expressed by an equation (1):                                                                         J                FN                            =                              A                ⁢                                  xe2x80x83                                ⁢                                  E                  2                                ⁢                                  xe2x80x83                                ⁢                exp                ⁢                                  xe2x80x83                                ⁢                                  (                                      -                                          B                      E                                                        )                                                                                                        =                                                (                                                                                    q                        3                                            ⁢                                              mE                        2                                                                                    8                      ⁢                                              xe2x80x83                                            ⁢                      π                      ⁢                                              xe2x80x83                                            ⁢                      Φ                      ⁢                                              xe2x80x83                                            ⁢                                              m                        xe2x80x2                                                                              )                                ⁢                                  xe2x80x83                                ⁢                exp                ⁢                                  xe2x80x83                                ⁢                                  (                                                                                    -                        8                                            ⁢                                              xe2x80x83                                            ⁢                      π                      ⁢                                              xe2x80x83                                            ⁢                                                                        (                                                      2                            ⁢                                                          m                              xe2x80x2                                                                                )                                                                          1                          /                          2                                                                    ⁢                                              xe2x80x83                                            ⁢                                              Φ                                                  3                          /                          12                                                                                                            3                      ⁢                                              xe2x80x83                                            ⁢                      hqE                                                        )                                                                                        (        1        )            
where q represents a unit electric charge, m represents a mass of electrons, E represents electric field strength applied to an oxide, h represents the Planck""s constant, "PHgr" represents a height of a barrier, and mxe2x80x2 represents an effective mass of electrons present in the tunnel oxide 4.
In the flash memory, exchange of electric charges between the floating gate 5 and the channel region in the case of using the FN tunnel phenomenon can be described by the above-stated current equation (1). Consequently, dispersion in the threshold voltage after executed the erasing operation and the writing operation depends on the dispersion of the FN tunnel current JFN. Therefore, larger dispersion of the FN tunnel current JFN indicate larger dispersion in the threshold voltage distribution after executed the erasing and the writing operation.
FIG. 16 shows a state of an energy bandgap of the memory cell structure of FIG. 9 (a channel is formed on the substrate 3) in the channel erasing operation. FIG. 17 shows a state of an energy bandgap of the memory cell structure of FIG. 9 in the channel writing operation. In each operation, tunneling of electrons through an energy barrier ("PHgr"FG in height) of the floating gate 5 or an energy barrier ("PHgr"sub in height) of the substrate 3 occurs, by which the electrons are emitted or injected. Consequently, a value of "PHgr" in the equation (1) is "PHgr"FG in channel erasing, and "PHgr"sub in channel writing. Specific values thereof shown in the reference 2 are as follows:
"PHgr"FG=2.3 to 2.95 (experimental value)
"PHgr"sub=2.7 to 2.8 (experimental value)
The reference 2 explains the reason why the height "PHgr" of the energy barriers and the level of dispersion are different. According to the explanation, the floating gate 5 is made of polysilicon, which causes segregation of phosphorous atoms on grain boundaries in an interface between the floating gate 5 and the tunnel oxide 4. This lowers the height "PHgr"SUB of the energy barrier, and generates dispersion of the threshold voltage. On contrary to this, the height "PHgr"SUB of the energy barrier is not lowered in the substrate 3. Therefore, the threshold voltage dispersion thereof is small.
The above description proves that in the two-step erasing method, tight control of the threshold voltage distribution is achievable since the channel erasing operation causing small dispersion of the threshold voltage is conducted after the channel writing operation causing large dispersion of the threshold voltage.
However, the conventional two-step erasing method for the ETOX-type flash memory cells has a following problem. The two-step erasing method disclosed in the reference 2 targets a flash memory of hundreds K bits, and therefore applying it to a flash memory LSI (Large Scale Integrated Circuit) actually in use requires a verifying operation of the threshold voltage.
FIG. 18 shows algorithm of a normal erasing operation applied to the conventional flash memory LSI. Generally, the erasing operation is executed per block. Upon start of the erasing operation, a pre-erasing program is performed in a step S1. As a result, threshold voltages of all the memory cells within an erasing-target block are set to be 5V or more. In a step S2, an erasing pulse is applied to all the memory cells within the erasing-target block. Application conditions of the erasing pulse are as shown in Table 2, according to which a voltage Vnn (ex., xe2x88x929V) is applied to the control gate 7, and a voltage Vesc (ex., +7V) is applied to the source 1 and the channel region, lowering the threshold voltage to 3V or less. In a step S3, verification of the threshold voltage is performed to verify if the threshold voltages of the memory cells within the erasing-target block are all set to be 3V or less. In a step S4, it is determined as a result of the threshold voltage verification if the threshold voltages of all the bits (memory cells) are 3V or less. If it is determined that the threshold voltages of all the bits are not 3V or less, the procedure returns to the step S2, and application of the erasing pulse is repeated. If it is determined that the threshold voltages of all the bits are 3V or less, the erasing operation of the block is terminated. Thus, application of the erasing pulse and verification are performed alternately as the erasing operation till the threshold voltages of all the bits become 3V or less. Such an erasing method is also disclosed in Japanese Patent Laid-Open Publication HEI No. 9-320282.
Next, description will be given of the normal erasing operation of the flash memory LSI shown in FIG. 18 with the two-step erasing method applied. FIG. 19 shows algbrism of applying the two-step erasing method to the normal erasing operation. In this case, the final object of the threshold voltage distribution after executed two-step erasing method is, as shown in FIG. 15, to be within the range of 0.5V to 2V.
In a step S11, a pre-erasing program is performed to set the threshold voltages of all the memory cells within an erasing-target block to 5V or more. In a step S12, an erasing pulse is applied (the first step). In a step S13, verification of the threshold voltage is performed. In a step S14, it is determined as a result of the threshold voltage verification if the threshold voltages of all the bits are 1.5V or less. If it is determined that the threshold voltages of all the bits are 1.5V or less, the procedure proceeds to a step S15. If not, the procedure returns to the step S12, and application of the erasing pulse is repeated. Thus, application of the erasing pulse and verification are performed alternately till the threshold voltages of all the bits are determined to be 1.5V or less.
In the step S15, a program pulse is applied (the second step). In a step S16, verification of the threshold voltage is performed. In a step S17, it is determined as a result of the threshold voltage verification if the threshold voltages of all the bits are 0.5V or more. If it is determined that the threshold voltages of all the bits are not 0.5V or more, the procedure returns to the step S15, and application of the program pulse is repeated. If it is determined that the threshold voltages of all the bits are 0.5V or more, the erasing operation of the block is terminated. Thus, application of the program pulse and verification are performed alternately as the erasing operation till the threshold voltages of all the bits become 0.5V or more.
The following description discusses a problem of the erasing operation shown in FIG. 19. FIG. 20 is a schematic view showing a memory cell array connected to one bit line BL in a NOR-type flash memory. Reference numeral M0, M1, M2, and M3 represent memory cells constituting a memory cell array. Drains of each memory cell M0, M1, M2, and M3 are connected to a common bit line BL, while sources thereof are connected to a common source line S. These memory cells M0, M1, M2, and M3 belong to the same block and accept collective erasing. A control gate of the memory cell M0 is connected to a word line WL0. Likewise, each control gate of the memory cells Ml, M2, and M3 is connected to word lines WL1, WL2, and WL3.
The bit line BL is connected to one input terminal of a sense amplifier SA. In the other input terminal of the sense amplifier SA, there is inputted a reference voltage Vref. The sense amplifier SA determines whether potential of the bit line BL is higher or lower than the reference voltage Vref, and outputs a voltage Vout indicating a determination result from an output terminal.
It is noted that FIG. 20 is simplified to describe the verifying operation in the erasing process. In reality, for writing and reading access to memory cells M, there is connected a voltage supply circuit for applying a writing voltage and a reading voltage to the bit line BL. There is also required a means for setting the bit line BL to a high impedance state in the erasing process. Description of these means are omitted in FIG. 20.
In FIG. 20, there is first performed a pre-erasing program (pre-erasing writing) of the memory cells M0 to M3 within a block according to the erasing operation algorism of FIG. 19. Consequently, the threshold voltages of the memory cells M0 to M3 are set to 5V or more. Next, after an erasing pulse is applied, verification is executed to verify whether the threshold voltages of all the memory cells M0 to M3 become 1.5V or less. Thereafter, application of the erasing pulse and verification are repeated. When the threshold voltages of the all the memory cells M0 to M3 within the block become 1.5V or less, the first step of the erasing operation is terminated. The operation stated hereinabove shall provide the threshold voltage distribution after the first step shown in FIG. 15.
However, the memory cells M have dispersion in erasing characteristics. Consequently, though the same erasing pulse is applied, some memory cells are fast in decrease of the threshold voltage (erase-fast memory cell), while some memory cells are slow in decrease of the threshold voltage (erase-slow memory cell), and these memory cells are mixed-present in the same block. It is assumed that a memory cell M3 in FIG. 20 is the most erase-fast memory cell, and a memory cell M0 is the most erase-slow memory cell.
As shown in FIG. 15, a distribution width of the threshold voltages of the memory cells M that are ago collectively erased within a block in the first step is approximately 2.5V. Therefore, if the most erase-slow memory cell MO obtains a threshold voltage of 2.3V as a result of being applied the erasing pulse once or plural times in the first step, the most erase-fast memory cell M3 obtains a negative threshold voltage of xe2x88x920.2V (=2.3V-2.5V).
In this state, verification is performed. In the verifying operation, word lines WLs are selected in sequence, and a voltage of 1.5V is applied to a selected word line WL, while a voltage of 0V is applied to unselected word lines WLs. In principle, when a word line WL0 is selected and a voltage of 1.5V is applied thereto, and a voltage of 0V is applied to unselected word lines WL1 to WL3, a cell current is not passed since the threshold voltage of the memory cell M0 is 2.3V as stated above. Accordingly, it is determined from the output voltage Vout of the sense amplifier SA that the threshold voltage of MO is 1.5V or more.
In reality, however, the threshold voltage of the memory cell M3 is xe2x88x920.2V, so that a word line WL3, though unselected (applied voltage is 0V), passes a cell current. As a result, even though the threshold voltage of the memory cell M0 is 2.3V, it is misdetermined to be 1.5V or less. This leads to a false determination that the first step is terminated.
In this case, with presence of the memory cell M0 having a threshold voltage of 2.3V, the procedure proceeds to the second step, where application of a program pulse is executed. As a result, a memory cell M having a threshold voltage of 2V or more is present after the second step, which disturbs the normal erasing operation. In the case where the normal two-step erasing is performed, the threshold voltage distribution is within the range of 0.5V to 2V, and the threshold voltages of all the memory cells M0 to M3 within the same block fall within 2V or less.
Accordingly, an object of the present invention is to provide an erasing method for a nonvolatile semiconductor memory device enabling normal erasing which makes a distribution of threshold voltages tight and within the range of 2V or less.
In order to achieve the above object, there is provided an erasing method for a nonvolatile semiconductor memory device comprising: floating-gate field-effect transistors, which have a control gate, a floating gate, a drain, and a source, and enable electric writing and erasing of information, disposed in a matrix configuration on a substrate or on a well; a plurality of row lines connected to the control gate of each floating-gate field-effect transistor arrayed in a row direction; and a plurality of column lines connected to the drain of each floating-gate field-effect transistor arrayed in a column direction, the source of each floating-gate field-effect transistor constituting a block being connected in common,
wherein the erasing operation is conducted in the block units with use of a Fowler-Nordheim tunneling phenomenon; and
comprises a first step for lowering threshold voltages of all the floating-gate field-effect transistors within the block to a voltage higher than 0, and equal to or lower than a first specified voltage in an erased state; a second step for lowering the threshold voltages to a voltage equal to or lower than a second specified voltage that is lower than the first specified voltage; and a third step for raising the threshold voltages to a voltage higher than 0.
According to the above structure, in the first step of erasing, the threshold voltages of all the floating-gate field-effect transistors within a block are lowered to a voltage higher than 0, and equal to or lower than a first specified voltage in an erased state. In that case, since each threshold voltage is higher than 0, it is possible to perform a verifying operation for a plurality of floating-gate field-effect transistors whose drains are connected on the same column line, and whose sources are connected in common, for verifying with accuracy that all the threshold voltages are in an erased state. In the second step, the threshold voltages are sufficiently lowered to a voltage equal to or lower than the second specified voltage that is lower than the first specified voltage. Accordingly, in the next third step, the threshold voltages are raised to a voltage higher than 0, which enables normal erasing in which a distribution of the threshold voltages is tight and falls within 2V or less.
In the second step, the verifying operation can be omitted since all the threshold voltages are already in an erased state in the first step. Therefore, even if the threshold voltage of an erase-fast floating-gate field-effect transistor is lowered to a negative value, a conventional problem relating to a false determination accompanied by the verifying operation does not occur.
In one embodiment of the present invention, the first step includes an applying operation of a first erasing pulse for lowering the threshold voltages, and a verifying operation for verifying lowered threshold voltages.
According to the above structure, the verifying operation is performed every time the first erasing pulse is applied to each of the floating-gate field-effect transistors. Application of the first erasing pulse is repeated till it is verified that each threshold voltage becomes equal to or less than the first specified voltage.
In one embodiment of the present invention, a reference voltage used in the verifying operation is higher than an upper limit voltage in a distribution of the threshold voltages finally obtained by the erasing operation.
According to the above structure, in the first step, an upper limit voltage in a distribution of the threshold voltages is set to be higher than an upper limit voltage in an distribution of the threshold voltages finally obtained by the erasing operation, which prevents a lower limit voltage from becoming a negative voltage. Thus, the verifying operation of a plurality of floating-gate field-effect transistors whose drains are connected on the same column line, and whose sources are connected in common is executed with accuracy.
In one embodiment of the present invention, the second step includes an applying operation of a second erasing pulse for lowering the threshold voltages, and excludes a verifying operation for verifying lowered threshold voltages.
According to the above structure, in the second step, the threshold voltages lowered in the first step are further lowered through application of a second erasing pulse. Therefore, even if the threshold voltage of an erase-fast floating-gate field-effect transistor is lowered to a negative value, a conventional problem relating to a false determination accompanied by the verifying operation does not occur.
In one embodiment of the present invention, number of application of the second erasing pulse is N (positive integer number) times as large as number of application of the first erasing pulse, and the threshold voltages upon termination of the second step are lower than an upper limit voltage in a distribution of the threshold voltages finally obtained by the erasing operation.
According to the above structure, in the second step, the second erasing pulse is applied N times as large as the number of application of the first erasing pulse, and the threshold voltages are set to be lower than an upper limit voltage in the threshold voltage distribution finally obtained by the erasing operation. Even without the verifying operation, specifying the optimum N value makes it possible that the threshold voltages, when raised in the next third step, provide a desired threshold voltage distribution.
In one embodiment of the present invention, assumed that number of application of the first erasing pulse is i, total application time of the second erasing pulse is (ixc3x97N) times as large as a pulse width of the first erasing pulse.
According to the above structure, in the second step, there is obtained an effect identical to that in the case where application of the second erasing pulse is conducted N times the number of application of the first erasing pulse.
In one embodiment of the present invention, the total application time of the second erasing pulse in the second step is divided by a pulse width of one or a plurality of the second pulses.
According to the above structure, in the second step, division number of the total application time of the above pulse is decreased so that the number of application of the second erasing pulse is reduced. This can eliminate a waste of time and power consumption due to charging and discharging of a well current, a source current, and a gate current.
In one embodiment of the present invention, the pulse width of the second erasing pulse by which the total application time of the pulse in the second step is divided is N times as large as a pulse width of the first erasing pulse, and pulse number of the second erasing pulse is i.
The above structure facilitates making the threshold voltage distribution tight and lower than a desired upper limit value.
In one embodiment of the present invention, the third step includes an applying operation of a writing pulse for raising the threshold voltages, and a verifying operation for verifying raised threshold voltages.
According to the above structure, the verifying operation is executed every time the writing pulse is applied to each of the floating-gate field-effect transistors. Application of the writing pulse is repeated till it is verified that each threshold voltage becomes higher than 0.
In one embodiment of the present invention, a reference voltage used in the verifying operation is a lower limit voltage in a distribution of the threshold voltages finally obtained by the erasing operation.
According to the above structure, in the third step, a lower limit voltage in a distribution of the threshold voltages is set with accuracy equal to or higher than a lower limit voltage in a distribution of the threshold voltages finally obtained by the erasing operation.
In one embodiment of the present invention, an absolute value of a pulse voltage of at least either the first erasing pulse or the second erasing pulse is raised by an absolute value of a specified voltage whenever application is executed.
According to the above structure, an absolute value of a voltage of the above erasing pulse is raised by an absolute value of a specified voltage whenever application is executed. Therefore, compared to the case of applying the erasing pulse with a constant voltage, time taken for lowering the threshold voltages to a specified voltage, and consequently erasing time are shortened.
In one embodiment of the present invention, absolute values of pulse voltages of the first erasing pulse and the second erasing pulse are raised whenever application is executed, an absolute value of a pulse voltage of the second erasing pulse applied first in the second step is a value obtained by adding an absolute value of the specified voltage to an absolute value of a pulse voltage of the first erasing pulse applied last in the first step.
According to the above structure, a simple processing of repeating the same procedure from the first step to the second step shortens time taken for lowering each threshold voltage to the second specified voltage or less.
In one embodiment of the present invention, lowering of the threshold voltages in the first step and the second step is implemented by pulling electrons from the floating gate of all the floating-gate field-effect transistors within the block toward a channel side.
According to the above structure, in the first and the second steps, so-called channel erasing is executed. Consequently, unlike the case of executing so-called source-side erasing which pulls electrons from a floating gate to a source side, there is no generation of a hot hole trap attributed to a BTBT current generated between the source and the well, resulting in improved reliability of memory cells composed of the floating-gate field-effect transistors.
In one embodiment of the present invention, raising of the threshold voltages in the third step is implemented by injecting electrons from a channel side to the floating gate of all the floating-gate field-effect transistors within the block.
According to the above structure, dispersion in the threshold voltage distribution generated by channel erasing in the first and the second steps is reduced by injection of electrons, i.e. a writing operation, from the channel side to the floating gate in the third step. Thus, erasing for obtaining a tight threshold voltage distribution is performed.